Many circuits are known for employing LSSD testing techniques, which are sensitive to a voltage level rather than to an edge of a pulse, but in general to provide a relatively complete test of a semiconductor circuit, such as a logic circuit of the processor type, very complex circuits must be used which require a large number of test pads or pins installed exclusively for test purposes. With modern technology requiring higher and higher circuit densities on a semiconductor chip, space is not readily available on a chip for large numbers of pads or pins or for complex testing circuitry.
In commonly assigned U.S. Pat. No. 4,488,259, filed by B. R. Mercy on Oct. 29, 1982, there is disclosed an LSSD chip monitor having input and output shift registers which reduce to some extent the number of input/output pads used for testing and/or controlling certain functions of a chip.
U.S. Pat. No. 3,771,131, filed on Apr. 17, 1972, by A. T. Ling, discloses a computer monitoring and diagnostics system that utilizes a register for latching data on test points located within a computer system.
U.S. Pat. No. 4,167,780, filed on Oct. 21, 1977, by H. Hayashy, discloses scan-in and scan-out registers used for carrying out a diagnostic check.
In an article entitled, "LSI Self-Test Using Level Sensitive Scan Design and Signature Analysis," by D. Komonytsky, Proceedings of the International Test Conference, 1982, pp. 414-424, there is described a method of built-in self-test using internally generated pseudo random patterns applied to chip primary inputs and internal shift register latches in Level Sensitive Scan Design.